This invention relates to a semiconductor apparatus and, in particular, to a redundancy circuit for repairing a defective memory cell and a semiconductor apparatus having the redundancy circuit.
Recently, a semiconductor apparatus is miniaturized and developed towards larger-scale integration. For example, in the field of a dynamic random access memory (hereinafter abbreviated to DRAM), products having a memory capacity of 1 Gbit are developed and put into practical use.
Such DRAM has a main memory cell array region in which a normal memory cell array is disposed and a redundancy circuit for repair in which a spare memory cell array region is disposed. In case where a defect is found in a part of the main memory cell array region, a defective memory cell is replaced by a spare memory cell. By the use of the redundancy circuit, the semiconductor apparatus integrated in a large scale is improved in yield and lowered in cost.
The redundancy circuit requires a programmable element for memorizing an address of the defective memory cell. As the programmable element, use is predominantly made of a breaking fuse comprising a polysilicon or a metal wire to be cut by a laser trimmer. However, such technique of cutting the fuse by the laser trimmer can not repair a defect after assembling the semiconductor apparatus. In view of the above, use is also made of an electric fuse, such as a capacitor fuse, capable of repairing the defect after assembling.
Repairing by the redundancy circuit is carried out in the following manner. At first, quality judgment of judging whether each product is defective or non-defective is carried out by the use of a tester to extract a defective memory cell. Next, the address of the defective memory cell is programmed into the fuse by the laser trimmer. Then, quality judgment is carried out again by the tester. In case of the electric fuse, the address of the defective memory cell is electrically programmed into the fuse. Thus, testing is carried out twice to extract the defective memory cell and to verify completion of repairing.
Such repairing using the electric fuse is disadvantageous in the following respect. A testing efficiency is low because testing is carried out twice. In the past, a testing time was short. It was therefore possible to carry out testing twice. However, the semiconductor apparatus integrated in a large scale and having a memory capacity on the order of 1 Gbit requires a long testing time. Further, testing is carried out taking into account mutual interference among a number of memory cells and therefore requires a testing time as long as several hours. Such long-time testing is carried out twice upon extracting the defective memory cell and upon verifying completion of repairing. This results in low testing efficiency and high cost.
In order to avoid the above-mentioned problem, it is proposed to carry out testing for verifying completion of repairing only in an area around the repaired memory cell so as to shorten the testing time. In this technique, however, the address of the memory cell to be repaired is different in each individual product. It is therefore necessary to individually test each product by the use of an individual test program. As compared with a current technique of simultaneously testing a plurality of products in parallel, the above-mentioned technique is disadvantageous in view of man-hour required in preparation of a plurality of test programs and a testing time. Thus, the problem of low testing efficiency due to two-times testing remains unsolved.
The redundancy circuit is disclosed in several related documents. Japanese Unexamined Patent application Publication (JP-A) No. H06-084393 (Patent Document 1) corresponding to U.S. Pat. No. 5,313,424 discloses a repairing circuit using an electric fuse. According to Japanese Unexamined Patent Application Publication (JP-A) No. 2003-338192 (Patent Document 2) corresponding to U.S. Patent Application Publication No. 2003-213954 A1, an address of a defective memory cell is latched in an I/O compression test. The latched address is programmed into an electrical fuse. Thereafter, a functional test is performed. According to Japanese Unexamined Patent Application Publication (JP-A) No. 2001-307497 (Patent Document 3) corresponding to U.S. Pat. No. 6,259,639 B1, a memory cell unit has a normal port and a test port. Upon a writing operation via the normal port, an address and data are latched. In a next cycle, data written via the test port in a preceding cycle is read and compared with the latched data. Upon detection of mismatching as a result of comparison, a defective cell is detected and the latched address and the latched data are used as redundant means. The address and the data are latched by software without using a fuse. When the redundant means is full, an overflow signal is produced.
In the above-mentioned patent documents 1 and 2, the problem of low testing efficiency is not yet solved. In the patent document 3, the test port is provided in addition to the normal port so that chip area overhead is large. Further, the patent document 3 discloses a repairing circuit without using a fuse, which is a technique different from this invention. None of these documents discloses any suggestion for solving the problem addressed by this invention, i.e., low testing efficiency due to testing carried out twice,
As described above, when the redundancy circuit is used, the quality judgment is at first carried out by the use of the tester to extract the defective memory cell. Next, the address of the defective memory cell is programmed into the fuse. Then, quality judgment is carried out again by the use of the tester. Thus, testing is carried out twice to detect the defective memory cell and to verify completion of repairing. This results in a problem of low testing efficiency.